schliessen

Filtern

 

Bibliotheken

Accelerating PQMRCGSTAB Algorithm on Xeon Phi

Utilizing iterative method to solve the large sparse linear systems is the key to many practical mathematical and physical problems. Recently, Intel released Xeon Phi, a many-core processor of Intel’s Many Integrated Core (MIC) architecture, comprises 60 cores and supports 512-bit SIMD operation. In... Full description

Journal Title: Advanced materials research 2013, Vol.709, p.555-562
Main Author: Chen, Cheng
Other Authors: Yang, Can Qun , Yao, Wen Ke , Qi, Jin , Wu, Qiang
Format: Konferenzbeitrag Konferenzbeitrag
Language: English
ID: ISSN: 1662-8985
Zum Text:
SendSend as email Add to Book BagAdd to Book Bag
Staff View
recordid: cdi_crossref_primary_10_4028_www_scientific_net_AMR_709_555
title: Accelerating PQMRCGSTAB Algorithm on Xeon Phi
format: Conference Proceeding
creator:
  • Chen, Cheng
  • Yang, Can Qun
  • Yao, Wen Ke
  • Qi, Jin
  • Wu, Qiang
ispartof: Advanced materials research, 2013, Vol.709, p.555-562
description: Utilizing iterative method to solve the large sparse linear systems is the key to many practical mathematical and physical problems. Recently, Intel released Xeon Phi, a many-core processor of Intel’s Many Integrated Core (MIC) architecture, comprises 60 cores and supports 512-bit SIMD operation. In this work, we aim at accelerating an iterative algorithm for large spare linear system, named PQMRCGSTAB, by using both Xeon Phi’s 8-way vector operation and dense threads. Then, we propose three optimizations to improve the performance: data prefetching to hide the data latency, vector register reusing, and SIMD-friendly reduction. Our experimental evaluation on Xeon Phi delivers a speedup of close to a factor 6 compared to the Intel Xeon E5-2670 octal-core CPU running the same problem.
language: eng
source:
identifier: ISSN: 1662-8985
fulltext: no_fulltext
issn:
  • 1662-8985
  • 1662-8985
url: Link


@attributes
NO1
SEARCH_ENGINEprimo_central_multiple_fe
SEARCH_ENGINE_TYPEPrimo Central Search Engine
RANK2.1712978
LOCALfalse
PrimoNMBib
record
control
sourceidcrossref
recordidTN_cdi_crossref_primary_10_4028_www_scientific_net_AMR_709_555
sourceformatXML
sourcesystemPC
sourcerecordid10_4028_www_scientific_net_AMR_709_555
originalsourceidFETCH-LOGICAL-c1777-2910467a59d510cf8b94679f2e5a961072017820299f023ed2c75716128453ae0
addsrcrecordideNqNz01LwzAYwPEgCs7pd-jJW7snWfN2EWrVKWw45wRvIWbpFulaSQLFb29EQfHk5Xm5_OGH0DmGogQiJsMwFME420XXOFN0Nk6qxargIAtK6QEaYcZILqSgh7_uY3QSwisAKzGhI5RXxtjWeh1dt82WD4tVPXtcV5dZ1W577-Jun_Vd9mzTWO7cKTpqdBvs2fceo6eb63V9m8_vZ3d1Nc8N5pznRGIoGddUbigG04gXmV7ZEEu1ZBg4AcwFASJlA2RqN8RwyjHDRJR0qi2M0cVX1_g-BG8b9ebdXvt3hUF94lXCqx-8SniV8CrhVcKnwNWfgHExGfsueu3a_2Y-ANXyadA
sourcetypeAggregation Database
isCDItrue
recordtypeconference_proceeding
display
typeconference_proceeding
titleAccelerating PQMRCGSTAB Algorithm on Xeon Phi
creatorChen, Cheng ; Yang, Can Qun ; Yao, Wen Ke ; Qi, Jin ; Wu, Qiang
creatorcontribChen, Cheng ; Yang, Can Qun ; Yao, Wen Ke ; Qi, Jin ; Wu, Qiang
descriptionUtilizing iterative method to solve the large sparse linear systems is the key to many practical mathematical and physical problems. Recently, Intel released Xeon Phi, a many-core processor of Intel’s Many Integrated Core (MIC) architecture, comprises 60 cores and supports 512-bit SIMD operation. In this work, we aim at accelerating an iterative algorithm for large spare linear system, named PQMRCGSTAB, by using both Xeon Phi’s 8-way vector operation and dense threads. Then, we propose three optimizations to improve the performance: data prefetching to hide the data latency, vector register reusing, and SIMD-friendly reduction. Our experimental evaluation on Xeon Phi delivers a speedup of close to a factor 6 compared to the Intel Xeon E5-2670 octal-core CPU running the same problem.
identifier
0ISSN: 1662-8985
1EISSN: 1662-8985
2DOI: 10.4028/www.scientific.net/AMR.709.555
languageeng
ispartofAdvanced materials research, 2013, Vol.709, p.555-562
lds50peer_reviewed
citedbyFETCH-LOGICAL-c1777-2910467a59d510cf8b94679f2e5a961072017820299f023ed2c75716128453ae0
citesFETCH-LOGICAL-c1777-2910467a59d510cf8b94679f2e5a961072017820299f023ed2c75716128453ae0
links
openurl$$Topenurl_article
thumbnail$$Usyndetics_thumb_exl
search
creatorcontrib
0Chen, Cheng
1Yang, Can Qun
2Yao, Wen Ke
3Qi, Jin
4Wu, Qiang
title
0Accelerating PQMRCGSTAB Algorithm on Xeon Phi
1Advanced materials research
descriptionUtilizing iterative method to solve the large sparse linear systems is the key to many practical mathematical and physical problems. Recently, Intel released Xeon Phi, a many-core processor of Intel’s Many Integrated Core (MIC) architecture, comprises 60 cores and supports 512-bit SIMD operation. In this work, we aim at accelerating an iterative algorithm for large spare linear system, named PQMRCGSTAB, by using both Xeon Phi’s 8-way vector operation and dense threads. Then, we propose three optimizations to improve the performance: data prefetching to hide the data latency, vector register reusing, and SIMD-friendly reduction. Our experimental evaluation on Xeon Phi delivers a speedup of close to a factor 6 compared to the Intel Xeon E5-2670 octal-core CPU running the same problem.
issn
01662-8985
11662-8985
fulltextfalse
rsrctypeconference_proceeding
creationdate2013
recordtypeconference_proceeding
recordideNqNz01LwzAYwPEgCs7pd-jJW7snWfN2EWrVKWw45wRvIWbpFulaSQLFb29EQfHk5Xm5_OGH0DmGogQiJsMwFME420XXOFN0Nk6qxargIAtK6QEaYcZILqSgh7_uY3QSwisAKzGhI5RXxtjWeh1dt82WD4tVPXtcV5dZ1W577-Jun_Vd9mzTWO7cKTpqdBvs2fceo6eb63V9m8_vZ3d1Nc8N5pznRGIoGddUbigG04gXmV7ZEEu1ZBg4AcwFASJlA2RqN8RwyjHDRJR0qi2M0cVX1_g-BG8b9ebdXvt3hUF94lXCqx-8SniV8CrhVcKnwNWfgHExGfsueu3a_2Y-ANXyadA
startdate201306
enddate201306
creator
0Chen, Cheng
1Yang, Can Qun
2Yao, Wen Ke
3Qi, Jin
4Wu, Qiang
scope
0AAYXX
1CITATION
sort
creationdate201306
titleAccelerating PQMRCGSTAB Algorithm on Xeon Phi
authorChen, Cheng ; Yang, Can Qun ; Yao, Wen Ke ; Qi, Jin ; Wu, Qiang
facets
frbrtype5
frbrgroupidcdi_FETCH-LOGICAL-c1777-2910467a59d510cf8b94679f2e5a961072017820299f023ed2c75716128453ae0
rsrctypeconference_proceedings
prefilterconference_proceedings
languageeng
creationdate2013
toplevelpeer_reviewed
creatorcontrib
0Chen, Cheng
1Yang, Can Qun
2Yao, Wen Ke
3Qi, Jin
4Wu, Qiang
collectionCrossRef
delivery
delcategoryRemote Search Resource
fulltextno_fulltext
addata
au
0Chen, Cheng
1Yang, Can Qun
2Yao, Wen Ke
3Qi, Jin
4Wu, Qiang
formatbook
genreproceeding
ristypeCONF
atitleAccelerating PQMRCGSTAB Algorithm on Xeon Phi
btitleAdvanced materials research
date2013-06
risdate2013
volume709
spage555
epage562
pages555-562
issn1662-8985
eissn1662-8985
abstractUtilizing iterative method to solve the large sparse linear systems is the key to many practical mathematical and physical problems. Recently, Intel released Xeon Phi, a many-core processor of Intel’s Many Integrated Core (MIC) architecture, comprises 60 cores and supports 512-bit SIMD operation. In this work, we aim at accelerating an iterative algorithm for large spare linear system, named PQMRCGSTAB, by using both Xeon Phi’s 8-way vector operation and dense threads. Then, we propose three optimizations to improve the performance: data prefetching to hide the data latency, vector register reusing, and SIMD-friendly reduction. Our experimental evaluation on Xeon Phi delivers a speedup of close to a factor 6 compared to the Intel Xeon E5-2670 octal-core CPU running the same problem.
doi10.4028/www.scientific.net/AMR.709.555